110 Volume I: RISC-V User-Level ISA V2.2
Pseudoinstruction Base Instruction(s) Meaning
la rd, symbol
auipc rd, symbol[31:12]
Load address
addi rd, rd, symbol[11:0]
l{b|h|w|d} rd, symbol
auipc rd, symbol[31:12]
Load global
l{b|h|w|d} rd, symbol[11:0](rd)
s{b|h|w|d} rd, symbol, rt
auipc rt, symbol[31:12]
Store global
s{b|h|w|d} rd, symbol[11:0](rt)
fl{w|d} rd, symbol, rt
auipc rt, symbol[31:12]
Floating-point load global
fl{w|d} rd, symbol[11:0](rt)
fs{w|d} rd, symbol, rt
auipc rt, symbol[31:12]
Floating-point store global
fs{w|d} rd, symbol[11:0](rt)
nop addi x0, x0, 0 No operation
li rd, immediate Myriad sequences Load immediate
mv rd, rs addi rd, rs, 0 Copy register
not rd, rs xori rd, rs, -1 One’s complement
neg rd, rs sub rd, x0, rs Two’s complement
negw rd, rs subw rd, x0, rs Two’s complement word
sext.w rd, rs addiw rd, rs, 0 Sign extend word
seqz rd, rs sltiu rd, rs, 1 Set if = zero
snez rd, rs sltu rd, x0, rs Set if 6= zero
sltz rd, rs slt rd, rs, x0 Set if < zero
sgtz rd, rs slt rd, x0, rs Set if > zero
fmv.s rd, rs fsgnj.s rd, rs, rs Copy single-precision register
fabs.s rd, rs fsgnjx.s rd, rs, rs Single-precision absolute value
fneg.s rd, rs fsgnjn.s rd, rs, rs Single-precision negate
fmv.d rd, rs fsgnj.d rd, rs, rs Copy double-precision register
fabs.d rd, rs fsgnjx.d rd, rs, rs Double-precision absolute value
fneg.d rd, rs fsgnjn.d rd, rs, rs Double-precision negate
beqz rs, offset beq rs, x0, offset Branch if = zero
bnez rs, offset bne rs, x0, offset Branch if 6= zero
blez rs, offset bge x0, rs, offset Branch if ≤ zero
bgez rs, offset bge rs, x0, offset Branch if ≥ zero
bltz rs, offset blt rs, x0, offset Branch if < zero
bgtz rs, offset blt x0, rs, offset Branch if > zero
bgt rs, rt, offset blt rt, rs, offset Branch if >
ble rs, rt, offset bge rt, rs, offset Branch if ≤
bgtu rs, rt, offset bltu rt, rs, offset Branch if >, unsigned
bleu rs, rt, offset bgeu rt, rs, offset Branch if ≤, unsigned
j offset jal x0, offset Jump
jal offset jal x1, offset Jump and link
jr rs jalr x0, rs, 0 Jump register
jalr rs jalr x1, rs, 0 Jump and link register
ret jalr x0, x1, 0 Return from subroutine
call offset
auipc x6, offset[31:12]
Call far-away subroutine
jalr x1, x6, offset[11:0]
tail offset
auipc x6, offset[31:12]
Tail call far-away subroutine
jalr x0, x6, offset[11:0]
fence fence iorw, iorw Fence on all memory and I/O
Table 20.2: RISC-V pseudoinstructions.